Calls the system to provide a service.
Note: The sc instruction is supported only in the PowerPC architecture.
The sc instruction causes a system call interrupt. The effective address (EA) of the instruction following the sc instruction is placed into the Save Restore Register 0 (SRR0). Bits 0, 5-9, and 16-31 of the Machine State Register (MSR) are placed into the corresponding bits of Save Restore Register 1 (SRR1). Bits 1-4 and 10-15 of SRR1 are set to undefined values.
The sc instruction has one syntax form. The syntax form does not affect the Machine State Register.
Note: The sc instruction has the same op code as the svc (Supervisor Call) instruction.
The svc (Supervisor Call) instruction.
Functional Differences for POWER and PowerPC Instructions .