| architecture |
Identifies the processor architecture. Valid values for AIX Version 4 are:
| POWER_RS |
Indicates a Power machine. |
| POWER_PC |
Indicates a PowerPC. |
|
| implementation |
Identifies the specific version of the processor. Each implementation is assigned a unique bit to allow for efficient checking of implementation sets. The following are examples of valid values (the header file contains more values):
| POWER_RS1 |
|
| POWER_RS2 |
|
| POWER_RSC |
|
| POWER_601 |
|
Two special values are also defined: POWER_RS_ALL and POWER_PC_ALL. These labels are defined as the bit OR of all members of their architecture. |
| version |
Identifies the central processing unit (CPU) version number. The following are examples of valid values (the header file contains more values):
| PV_RS1 |
Identifies a Power RS1 machine. |
| PV_RS2 |
Identifies a Power RS2 machine. |
| PV_RS2G |
Identifies a Power RS2 machine with graphics assist. |
| PV_RSC |
Identifies a Power RSC machine. |
| PV_601 |
Identifies a Power PPC 601 machine. |
|
| width |
Contains the processor data-word size. Valid values are 32 or 64. This value is the maximum data-word size and should not be confused with the current execution mode. |
| ncpus |
Identifies the number of CPUs active on a machine. Uniprocessor (UP) machines are identified by a 1. Values greater than 1 indicate multiprocessor (MP) machines. |
| cache_attr |
Specifies the cache attributes. Bit 31 determines if the cache is present. If this bit is 1, the cache is present. If bit 31 is 0, then no cache is present and all other cache characteristics are 0. Bit 30 indicates the type of cache. If bit 30 is 1, the cache is combined. Otherwise, if bit 30 is 0 the instruction and data caches are separate. |
| icache_size |
Contains the L1 instruction-cache size in bytes. For combined caches, this value is the total cache size. |
| dcache_size |
Contains the size of the L1 data-cache size in bytes. For combined caches this the total cache size. |
| icache_asc |
Contains the L1 instruction-cache associativity. For a combined cache, this is the combined caches' associativity. |
| dcache_asc |
Contains the L1 data-cache associativity. For a combined cache, this is the combined caches' associativity. |
| icache_line |
Contains the line size in bytes of the L1 instruction cache. |
| dcache_line |
Contains the line size in bytes of L1 data cache. |
| L2_cache_size |
Contains the size of the L2 cache in bytes. A value of 0 indicates no L2 cache is present. |
| L2_cache_asc |
Identifies the associativity of the L2 cache. |
| tlb_comb |
Identifies the type of Transaction Lookaside Buffer (TLB) attributes. If the TLB is present, bit 31 is 1. Otherwise, if bit 31 is less than 0, the TLB does not exist and all other TLB characteristics are 0. Bit 30 is 1 if the TLB is combined. If the TLB is separate for the instruction and data cache, bit 30 is 0. |
| itlb_size |
Specifies the number of entries in the instruction TLB. For combined TLBs, this is the size of the combined TLB. |
| dtlb_size |
Specifies the number of entries in the data TLB. For combined TLBs, this is the size of the combined TLB. |
| itlb_asc |
Contains the associativity of the instruction TLB. This attribute's value is equal to the itlb_size attribute if the system is fully associative. |
| dtlb_asc |
Contains the associativity of the instruction TLB. This attribute's value is equal to the value of the dtlb_size attribute if the system is fully associative. |
| resv_size |
Contains the PowerPC reservation granule size. This field is a 0 on Power machines. |
| priv_ick_cnt |
Contains the number of times lock services attempt to lock a spin lock before blocking AP process/thread in supervisor mode. This a 0 on UP machine. This parameter is used by system-locking services. |
| prob_lck_cnt |
Contains the number of times lock services attempt to lock a spin lock before blocking a process or thread in problem state. This a 0 on a UP machine. This parameter is used by system-locking services. |
| virt_alias |
Indicates virtual memory aliasing. If 1, the hardware is available for virtual memory aliasing and this ability is used by the system. Virtual memory aliasing is the mapping of one real address to more than one virtual address. |
| cach_cong |
Contains the number page index bits that can result in a cache synonym. For machines without cache synonyms, this field is 0. |