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Assembler Language Reference

fcfid (Floating Convert from Integer Double Word) Instruction

Purpose

Convert the fixed-point contents of a floating-point register to a double-precision floating-point number.

Syntax

PowerPC
fcfid FRT, FRB (Rc=0)
fcfid. FRT, FRB (Rc=1)

Description

The 64-bit signed fixed-point operand in floating-point register (FPR) FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision using the rounding mode specified by FPSCR[RN] and placed into FPR FRT.

FPSCR[FPRF] is set to the class and sign of the result. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact.

The fcfid instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

Syntax Form Floating-Point Status and Control Register Record Bit (Rc) Condition Register Field 1
fcfid FPRF,FR,FI,FX,XX 0 None
fcfid. FPRF,FR,FI,FX,XX 1 FX,FEX,VX,OX

Parameters

FRT Specifies the target floating-point register for the operation.
FRB Specifies the source floating-point register for the operation.

Implementation

This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.


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